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? semiconductor components industries, llc, 2012 may, 2012 ? rev. 1 1 publication order number: ncv7425/d ncv7425 lin transceiver with voltage regulator and reset pin general description the ncv7425 is a fully featured local interconnect network (lin) transceiver designed to interface between a lin protocol controller and the physical bus. the ncv7425 lin device is a member of the in ? vehicle networking (ivn) transceiver family of on semiconductor that integrates a lin v2.1 physical transceiver and a low ? drop voltage regulator. it is designed to work in harsh automotive environment and is submitted to the ts16949 qualification flow. the lin bus is designed to communicate low rate data from control devices such as door locks, mirrors, car seats, and sunroofs at the lowest possible cost. the bus is designed to eliminate as much wiring as possible and is implemented using a single wire in each node. each node has a slave mcu ? state machine that recognizes and translates the instructions specific to that function. the main attraction of the lin bus is that all the functions are not time critical and usually relate to passenger comfort. features ? lin ? bus t ransceiver ? lin compliant to specification revision 2.1 (backward compatible to versions 2.0 and 1.3) and j2602 ? bus voltage 45 v ? transmission rate up to 20 kbaud ? integrated slope control for improved emi compatibility ? package ? soic ? 16 wide body green package with exposed pad ? protection ? thermal shutdown ? indefinite short ? circuit protection on pins lin and wake towards supply and ground ? load dump protection (45 v) ? bus pins protected against transients in an automotive environment ? esd protection level for lin, inh, wake and v bb up to 10 kv ? voltage regulator ? two device versions: output voltage 3.3 v or 5 v for loads up to 150 ma ? under ? voltage detector with a reset output to the supplied microcontroller ? inh output for auxiliary purposes (switching of an external pull ? up or resistive divider towards battery, control of an external voltage regulator etc.) ? modes ? normal mode: lin communication in either low (up to 10 kbaud) or normal slope ? sleep mode: v cc is switched ?off? and no communication on lin bus ? stand ? by mode: v cc is switched ?on? but there is no communication on lin bus ? wake ? up bringing the component from sleep mode into standby mode is possible either by lin command or digital input signal on wake pin wake ? up from lin bus can also be detected and flagged when the chip is already in standby mode ? these are pb ? free devices typical applications ? automotive ? industrial networks soic ? 16 lead wide body exposed pad case 751ag marking diagram ncv7425 ? x awlyywwg 1 16 1 16 http://onsemi.com x = 0 or 5 a = assembly location wl = wafer lot yy = year ww = work week g = pb ? free package see detailed ordering and shipping information in the package dimensions section on page 19 of this data sheet. ordering information
ncv7425 http://onsemi.com 2 table 1. key technical characteristics symbol parameter min typ max unit 3.3 v version v bb nominal battery operating voltage 5 12 28 v v bb load dump protection (note 1) 45 v i bb _slp supply current in sleep mode 20 a v cc_out (note 2) regulated v cc output in normal mode, v cc load 0 ? 100 ma 3.234 3.3 3.366 v regulated v cc output in normal mode, 100 ma < v cc load < 150 ma 3.201 3.3 3.399 i out_lim v cc regulator current limitation 150 225 300 ma v wake operating dc voltage on wake pin 0 v bb v maximum rating voltage on wake pin ? 45 45 v inh operating dc voltage on inh pin 0 v bb v t j_tsd junction thermal shutdown temperature 165 195 c t j operating junction temperature ? 40 +150 c 5 v version v bb nominal battery operating voltage 6 12 28 v v bb load dump protection (note 1) 45 v i bb_slp supply current in sleep mode 20 a v cc_out (note 2) regulated v cc output in normal mode, v cc load 0 ? 100 ma 4.90 5 5.10 v regulated v cc output in normal mode, 100 ma < v cc load < 150 ma 4.85 5 5.15 v i out_lim v cc regulator current limitation 150 225 300 ma v wake operating dc voltage on wake pin 0 v bb v maximum rating voltage on wake pin ? 45 45 v inh operating dc voltage on inh pin 0 v bb v t j_tsd junction thermal shutdown temperature 165 195 c t j operating junction temperature ? 40 +150 c 1. the applied transients shall be in accordance with iso 7637 part 1, test pulse 5. the device complies with functional class c ;. the lin communication itself complies with functional class b. on regulator class a can be reached depending on the application and ext ernal components 2. v cc voltage must be properly stabilized by external capacitors: capacitor of min. 80 nf with esr < 10 m in parallel with a capacitor of min. 8 f, esr < 1 . table 2. thermal characteristics symbol parameter conditions value unit r th(vj ? a)_1 thermal resistance junction ? to ? ambient on jedec 1s0p pcb free air 138 k/w r th(vj ? a)_2 thermal resistance junction ? to ? ambient on jedec 1s0p + 300 mm 2 pcb free air 94 k/w r th(vj ? a)_3 thermal resistance junction ? to ? ambient on jedec 2s2p pcb free air 70 k/w r th(vj ? a)_4 thermal resistance junction ? to ? ambient on jedec 2s2p + 300 mm 2 pcb free air 49 k/w
ncv7425 http://onsemi.com 3 pd20090609 .1 stb v cc txd v cc en v cc rstn rxd v cc wake control logic ncv7425 lin timeout slope control receiver gnd thermal shutdown osc v bb v bb v bb inh v cc v ? reg band ? gap test otp _zap por v bb v cc figure 1. block diagram typical application application information the emc immunity of the master ? mode device can be further enhanced by adding a capacitor between the lin output and ground. the optimum value of this capacitor is determined by the length and capacitance of the lin bus, the number and capacitance of slave devices, the pull ? up resistance of all devices (master and slave), and the required time constant of the system, respectively. v cc voltage must be properly stabilized by external capacitors: capacitor of min. 80 nf (esr < 10 m ) in parallel with a capacitor of min. 8 f (esr < 1 ). the 10 f capacitor on the battery is optional and serves as reservoir capacitor to deal with battery supply micro ? cuts. kl30 lin ? bus kl31 lin master node 1nf 1k gnd ncv 7425 micro controller rxd txd en stb gnd inh v bb vbat gnd 10nf wake lin slave node 220 pf gnd micro controller vbat gnd wake 10uf 100nf v cc v cc 10uf 100nf rstn test otp_zap 10nf rxd txd en stb gnd inh v bb v cc rstn test otp_zap lin wake 10uf 100nf 10uf 100nf v cc lin wake pd20090609.2 figure 2. application diagram
ncv7425 http://onsemi.com 4 figure 3. pin assignment 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v bb v cc lin gnd gnd wake inh otp_sup n.c. rxd txd rstn stb en test n.c. ncv7425 table 3. pin function description pin number pin name description 1 v bb battery supply input 2 lin lin bus output/input 3 gnd ground 4 gnd ground 5 wake high voltage digital input pin to switch the part from sleep ? to standby mode 6 inh inhibit output 7 otp_sup supply for programming of trimming bits at factory testing, needs to be grounded in the application 8 n.c. not connected 9 n.c. not connected 10 test digital input for factory testing, needs to be grounded in the application 11 en enable input for mode control 12 stb standby mode control input 13 rstn reset output; open ? drain output with an on ? chip pull ? up resistor 14 txd transmit data input, low in dominant state 15 rxd receive data output; low in dominant state; push ? pull output 16 v cc voltage regulator output functional description overall functional description lin is a serial communication protocol that efficiently supports the control of mechatronic nodes in distributed automotive applications. the domain is class ? a multiplex buses with a single master node and a set of slave nodes. ncv7425 is designed as a master or slave node for the lin communication interface with an integrated 3.3 v or 5 v voltage regulator having a current capability up to 150 ma for supplying any external components (microcontroller, can node, etc.). ncv7425 contains the lin transmitter, lin receiver, voltage regulator, power ? on ? reset (por) circuits and thermal shutdown (tsd). the lin transmitter is optimized for the maximum specified transmission speed of 20 kbaud with emc performance due to reduced slew rate of the lin output. the junction temperature is monitored via a thermal shutdown circuit that switches the lin transmitter and voltage regulator off when temperature exceeds the tsd trigger level. ncv7425 has four operating states (normal mode, low slope mode, stand ? by mode, and sleep mode) that are determined by the input signals en, wake, stb, and txd. operating states ncv7425 provides four operating states, two modes for normal operation with communication, one stand ? by without communication and one low power mode with very low current consumption ? see figure 4 and table 4.
ncv7425 http://onsemi.com 5 table 4. mode selection mode v cc rxd inh lin transceiver 30 k on lin rstn normal ? slope (note 3) on low = dominant state high = recessive state high if stb = high during state transition; floating otherwise normal slope on high normal ? low slope (note 4) on low = dominant state high = recessive state high if stb = high during state transition; floating otherwise low slope on high stand ? by (note 5) on low after lin wake ? up, high otherwise (note 6) floating off off controlled by v cc under ? voltage monitor sleep off clamped to v cc (note 6) floating off off low 3. the normal slope mode is entered when pin en goes high while txd is in high state during en transition. 4. the low slope mode is entered when pin en goes high while txd is in low state during en transition. lin transmitter gets on o nly after txd returns to high after the state transition. 5. the stand ? by mode is entered automatically after power ? up. 6. in stand ? by and sleep mode, the high state is achieved by internal pull ? up resistor to v cc . standby mode ? ? lin trx: off ? inh: floating ? lin term.: current source ? rxd pin: high/low ? rstn pin: normal mode (normal slope ) ? ? lin trx: on ? inh: high/floating ? lin term.: 30k ? rxd pin: lin data ? rstn pin: high normal mode (low slope ) ? ? lin trx: on ? inh: high/floating ? lin term.: 30k ? rxd pin: lin data ? rstn pin: high sleep mode ? ? lin trx: off ? inh: floating ? lin term.: current source ? rxd pin: ? rstn pin: low en changes 0 ? >1 while txd=1 en changes 1 ? >0 while stb=1 en changes 0 ? >1 while txd=0 en changes 1 ? >0 while stb=1 en changes 1 ? >0 while stb=0 en changes 1 ? >0 while stb=0 pd20090610 .01 figure 4. state diagram v cc under ? voltage v cc_uv v cc : on v cc : on v cc : on v cc : off at v cc v cc under ? voltage v bb power ? up normal slope mode in normal slope mode the transceiver can transmit and receive data via lin bus with speed up to 20 kbaud. the transmit data stream of the lin protocol is present on the txd pin and converted by the transmitter into a lin bus signal with controlled slew rate to minimize emc emission. the receiver consists of the comparator that has a threshold with hysteresis in respect to the supply voltage and an input filter to remove bus noise. the lin output is pulled high via an internal 30 k pull ? up resistor. for master applications it is needed to put an external 1 k resistor with a serial diode between lin and v bb (or inh) ? see figure 2. the mode selection is done by en=high when txd pin is high. if stb pin is high during the standby ? to ? normal slope mode transition, inh pin is pulled high. otherwise, it stays floating. low slope mode in low slope mode the slew rate of the signal on the lin bus is reduced (rising and falling edges of the lin bus signal are longer). this further reduces the emc emission. as a consequence the maximum speed on the lin bus is reduced up to 10 kbaud. this mode is suited for applications where the communication speed is not critical. the mode selection
ncv7425 http://onsemi.com 6 is done by en=high when txd pin is low. in order not to transmit immediately a dominant state on the bus (because txd = low), the lin transmitter is enabled only after txd returns to high. if stb pin is high during the standby ? to ? low slope mode transition, inh pin is pulled high. otherwise, it stays floating. stand ? by mode the stand ? by mode is always entered after power ? up of the ncv7425. it can also be entered from normal mode when the en pin is low and the stand ? by pin is high. from sleep mode it can be entered after a local wake ? up or lin wakeup. in stand ? by mode the v cc voltage regulator for supplying external components (e.g. a microcontroller) stays active. also the lin receiver stays active to be able to detect a remote wake ? up via bus. the lin transmitter is disabled and the slave internal termination resistor of 30 k between lin and v bb is disconnected in order to minimize current consumption. only a pull ? up current source between v bb and lin is active. sleep mode the sleep mode provides extremely low current consumption. this mode is entered when both en and stb pins are low coming from normal mode. the internal termination resistor of 30 k between lin and v bb is disconnected and also the v cc regulator is switched off to minimize current consumption. wake ? up ncv7425 has two possibilities to wake ? up from sleep or stand ? by mode (see figure 4): local wake ? up: enables the transition from sleep mode to stand ? by mode remote wake ? up via lin: enables the transition from sleep ? to stand ? by mode and can be also detected when already in standby mode. a local wake ? up is only detected in sleep mode if a transition from low to high or from high to low is seen on the wake pin. wake t v bb detection of local wake ? up sleep mode stand ? by mode 50% v bb typ. wake t v bb detection of local wake ? up sleep mode stand ? by mode pc20060427.3 50% v bb typ. figure 5. local wake ? up signal a remote wake ? up is only detected if a combination of (1) a falling edge at the lin pin (transition from recessive to dominant) is followed by (2) a dominant level maintained for a time period > t wake and (3) again a rising edge at pin lin (transition from dominant to recessive) happens. lin recessive level lin t t wake detection of remote wake ? up sleep mode stand ? by mode lin dominant level pc20060427.2 figure 6. remote wake ? up behavior v bb 40% v bb 60% v bb the wake ? up source is distinguished by pin rxd in the stand ? by mode: rxd remains high after power ? up or local wake ? up. rxd is kept low until normal mode is entered after a remote wake ? up (lin) v cc under ? voltage detection and rstn pin in standby, normal and low ? slope modes, the v cc regulator is monitored. whenever the regulator output falls below v cc_uv_thr level (typically 90% of the nominal voltage) for longer than v cc_uv_deb (typically 5 s), an
ncv7425 http://onsemi.com 7 under ? voltage is detected. output pin rstn is pulled to low level to indicate the under ? voltage condition to the external load (a microcontroller). at the same time, the device enters automatically the standby mode. as soon as the regulator output returns above the under ? voltage level, the rstn low level is extended by typically 6ms and only then released to high level in order to ensure microcontroller initialization under correct supply conditions. in the sleep mode, rstn pin is kept low regardless the v cc level ? it means that rstn becomes low immediately at sleep mode entry even if the v cc capacitor is still char ged. in all situations where rstn pin is kept low, the digital inputs to ncv7425 are discarded by the internal control logic and have no effect on its behavior. the rstn pin function is illustrated in figure 7. figure 7. rstn pin behavior
ncv7425 http://onsemi.com 8 electrical characteristics definitions all voltages are referenced to gnd. positive currents flow into the ic. table 5. absolute maximum ratings ? 3.3 v and 5 v versions symbol parameter min. max. unit v bb battery voltage on pin v bb (note 7) ? 0.3 +45 v v cc dc voltage on pin v cc 0 +6 v i vcc current delivered by the v cc regulator 150 ma v lin lin bus voltage (note 8) ? 45 +45 v v inh dc voltage on inhibit pin ? 0.3 v bb + 0.3 v v wake voltage on wake pin ? 45 45 v v dig_io dc voltage on pins txd, rxd, en, stb, rstn ? 0.3 v cc + 0.3 v t j maximum junction temperature ? 40 +165 c v esd electrostatic discharge voltage (inh, wake and v bb ) system human body model (hbm) (note 9) ? 10 +10 kv electrostatic discharge voltage (lin pin, no external capacitor) hbm (note 9) ? 10 +10 electrostatic discharge voltage (lin pin, 220 pf) system hbm (note 9) ? 15 +15 electrostatic discharge voltage (pins lin, inh, wake and v bb ) hbm (note 10) ? 8 +8 electrostatic discharge voltage (other pins) hbm (note 10) ? 4 +4 electrostatic discharge voltage; charge device model (note 11) ? 250 +250 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 7. the applied transients shall be in accordance with iso 7637 part 1, test pulses 1, 2, 3a, 3b, and 5. the device complies with functional class c; class a can be reached depending on the application and external components. 8. the applied transients shall be in accordance with iso 7637 part 1, test pulses 1, 2, 3a, and 3b. the device complies with fu nctional class c; class a can be reached depending on the application and external components. 9. equivalent to discharging a 150 pf capacitor through a 330 resistor conform to iec standard 61000 ? 4 ? 2. the specified values are verified by external test house. 10. equivalent to discharging a 100 pf capacitor through a 1.5 k resistor conform to mil std 883 method 3015.7. 11. conform to eos/esd ? ds5.3 (socket mode). table 6. dc characteristics ? 3.3 v version v bb = 5 v to 28 v; t j = ? 40 c to +150 c; unless otherwise specified. symbol parameter conditions min typ max unit dc characteristics supply ? pins v bb and v cc i bb_on supply current normal mode; lin recessive 1.6 ma i bb_stb supply current stand ? by mode, v bb = 5 ? 18 v, t j < 105 c 60 a i bb_slp supply current sleep mode, v bb = 5 ? 18 v, t j < 105 c 20 a dc characteristics ? voltage regulator v cc_out regulator output voltage v cc load 0 ? 100 ma 3.234 3.30 3.366 v 100 ma < v cc load < 150 ma 3.201 3.30 3.399 12. measured at output voltage v cc_out = (v cc_out @ v bb = 5 v) ? 2%. 13. the voltage drop in normal mode between lin and v bb pin is the sum of the diode drop and the drop at serial pull up resistor. the drop at the switch is negligible. see figure 2. 14. guaranteed by design. not tested
ncv7425 http://onsemi.com 9 table 6. dc characteristics ? 3.3 v version v bb = 5 v to 28 v; t j = ? 40 c to +150 c; unless otherwise specified. symbol unit max typ min conditions parameter dc characteristics ? voltage regulator i out_lim over ? current limitation 150 225 300 ma v cc_uv_thr under ? voltage detection threshold 2.80 2.97 3.13 v v cc_out line regulation v bb 5 ? 28 v, i out = 5 ma t j = 25 c 0.41 mv load regulation i out 1 ? 100 ma, v bb = 14 v, t j = 25 c 25 v do dropout voltage (v bb ? v cc_out ) (note 12) figure 12 i out = 10 ma, t j = 25 c 22 mv i out = 50 ma, t j = 25 c 108 i out = 100 ma, t j = 25 c 216 dc characteristics ? lin transmitter v lin_dom_losup lin dominant output voltage txd = low; v bb = 7.3 v 1.2 v v lin_dom_hisup lin dominant output voltage txd = low; v bb = 18 v 2.0 v v ser_diode lin voltage drop at serial diode (note 13) txd = high; i lin = 10 a 0.3 1 v i lin_lim short circuit current limitation v lin = v bb(max) 40 200 ma r slave internal pull ? up resistance 20 33 47 k c lin capacitance on pin lin (note 14) 25 35 pf i lin_off_dom lin output current bus in dominant state driver off; v bb = 12 v ? 1 ma i lin_off_rec lin output current bus in recessive state driver off; v bb < 18 v, v bb < v lin < 18 v 1 a i lin_no_gnd communication not affected v bb = gnd = 12 v; 0 < v lin < 18 v ? 1 1 ma i lin_no_vbb lin bus remains operational v bb = gnd = 0 v; 0 < v lin < 18 v 5 a dc characteristics ? lin receiver v bus_dom bus voltage for dominant state 0.4 v bb v bus_rec bus voltage for recessive state 0.6 v bb v rec_dom receiver threshold lin bus recessive dominant 0.4 0.6 v bb v rec_rec receiver threshold lin bus dominant recessive 0.4 0.6 v bb v rec_cnt receiver centre voltage (v bus_dom + v bus_rec ) / 2 0.475 0.525 v bb v rec_hys receiver hysteresis 0.05 0.175 v bb dc characteristics ? digital i/o pins pin wake v wake_th threshold voltage 0.35 0.65 v bb il eak input leakage current v wake = 0 v; v bb = 18 v ? 1 ? 0.5 1 a t wake(min) debounce time sleep mode; rising and falling edge 8 54 s pins txd and stb v il low level input voltage 0.8 v 12. measured at output voltage v cc_out = (v cc_out @ v bb = 5 v) ? 2%. 13. the voltage drop in normal mode between lin and v bb pin is the sum of the diode drop and the drop at serial pull up resistor. the drop at the switch is negligible. see figure 2. 14. guaranteed by design. not tested
ncv7425 http://onsemi.com 10 table 6. dc characteristics ? 3.3 v version v bb = 5 v to 28 v; t j = ? 40 c to +150 c; unless otherwise specified. symbol unit max typ min conditions parameter dc characteristics ? digital i/o pins pins txd and stb v ih high level input voltage 2.0 v r pu pull ? up resistance to v cc 50 200 k pin inh delta_v h high level voltage drop i inh = 15 ma 0.35 0.75 v i leak leakage current sleep mode; v inh = 0 v ? 1 1 a pin en v il low level input voltage 0.8 v v ih high level input voltage 2.0 v r pd pull ? down resistance to ground 50 200 k pin rxd v ol low level output voltage i sink = 2 ma 0.65 v v oh high level output voltage (in normal mode) normal mode, i source = ? 2 ma v cc ? 0.65 v r pu pull ? up resistance to v cc (in standby and sleep mode) standby mode, sleep mode 10 k pin rstn v ol low level output voltage i sink = 2 ma 0.65 v r pu pull ? up resistance to v cc 50 200 k dc characteristics power ? on reset por h_vbb v bb por high level detection threshold 4.5 v por l_vbb v bb por low level detection threshold 1.7 3.8 v por _vbb_sl maximum slope on v bb to guarantee por 2 v/ s thermal shutdown t j_tsd junction temperature for shutdown 165 195 c t j_hyst thermal shutdown hysteresis 9 18 c 12. measured at output voltage v cc_out = (v cc_out @ v bb = 5 v) ? 2%. 13. the voltage drop in normal mode between lin and v bb pin is the sum of the diode drop and the drop at serial pull up resistor. the drop at the switch is negligible. see figure 2. 14. guaranteed by design. not tested
ncv7425 http://onsemi.com 11 table 7. dc characteristics ? 5 v version v bb = 6 v to 28 v; t j = ? 40 c to +150 c; unless otherwise specified. symbol parameter conditions min typ max unit dc characteristics supply ? pins v bb and v cc i bb_on supply current normal mode; lin recessive 1.6 ma i bb_stb supply current stand ? by mode, v bb = 6 ? 18 v, t j < 105 c 60 a i bb_slp supply current sleep mode, v bb = 6 ? 18v, t j < 105 c 20 a dc characteristics ? voltage regulator v cc_out regulator output voltage v cc load 0 ? 100 ma 4.9 5 5.1 v 100 ma < v cc load < 150 ma 4.85 5 5.15 v i out_lim over ? current limitation 150 225 300 ma v cc_uv_thr under ? voltage detection threshold 4.25 4.5 4.75 v v cc_out line regulation v bb 6 ? 28 v, i out = 5 ma t j = 25 c 0.41 mv load regulation i out 1 ? 100 ma, v bb = 14 v, t j = 25 c 22 mv v do dropout voltage (v bb ? v cc_out ) (note 15) (figure 20) i out = 10 ma, t j = 25 c 22 mv i out = 50 ma, t j = 25 c 108 mv i out = 100 ma, t j = 25 c 216 mv dc characteristics lin transmitter v lin_dom_losup lin dominant output voltage txd = low; v bb = 7.3 v 1.2 v v lin_dom_hisup lin dominant output voltage txd = low; v bb = 18 v 2.0 v v ser_diode lin voltage drop at serial diode (note 16) txd = high; i lin = 10 a 0.3 1 v i lin_lim short circuit current limitation v lin = v bb(max) 40 200 ma r slave internal pull ? up resistance 20 33 47 k c lin capacitance on pin lin (note 17) 25 35 pf i lin_off_dom lin output current bus in dominant state driver off; v bb = 12 v ? 1 ma i lin_off_rec lin output current bus in recessive state driver off; v bb < 18 v, v bb < v lin < 18 v 1 a i lin_no_gnd communication not affected v bb = gnd = 12 v; 0 < v lin < 18 v ? 1 1 ma i lin_no_vbb lin bus remains operational v bb = gnd = 0 v; 0 < v lin < 18 v 5 a dc characteristics lin receiver v bus_dom bus voltage for dominant state 0.4 v bb v bus_rec bus voltage for recessive state 0.6 v bb v rec_dom receiver threshold lin bus recessive dominant 0.4 0.6 v bb v rec_rec receiver threshold lin bus dominant recessive 0.4 0.6 v bb v rec_cnt receiver center voltage (v bus_dom + v bus_rec ) / 2 0.475 0.525 v bb v rec_hys receiver hysteresis 0.05 0.175 v bb 15. measured at output voltage v cc_out = (v cc_out @ v bb = 6 v) ? 2%. 16. the voltage drop in normal mode between lin and v bb pin is the sum of the diode drop and the drop at serial pull up resistor. the drop at the switch is negligible. see figure 2. 17. guaranteed by design. not tested
ncv7425 http://onsemi.com 12 table 7. dc characteristics ? 5 v version v bb = 6 v to 28 v; t j = ? 40 c to +150 c; unless otherwise specified. symbol unit max typ min conditions parameter dc characteristics ? digital i/o pins pin wake v wake_th threshold voltage 0.35 0.65 v bb i leak input leakage current v wake = 0 v; v bb = 18 v ? 1 ? 0.5 1 a t wake_min debounce time sleep mode; rising and falling edge 8 54 s pins txd and stb v il low level input voltage 0.8 v v ih high level input voltage 2.0 v r pu pull ? up resistance to v cc 50 200 k pin inh delta_vh high level voltage drop i inh = 15 ma 0.35 0.75 v i_leak leakage current sleep mode; v inh = 0 v ? 1 1 a pin en v il low level input voltage 0.8 v v ih high level input voltage 2.0 v r pd pull ? down resistance to ground 50 200 k pin rxd v ol low level output voltage i sink = 2 ma 0.65 v v oh high level output voltage (in normal mode) normal mode, i source = ? 2 ma v cc ? 0.65 v r pu pull ? up resistance to v cc (in standby and sleep mode) standby mode, sleep mode 10 k pin rstn v ol low level output voltage i sink = 2 ma 0.65 v r pu pull ? up resistance to v cc 50 200 k dc characteristics power ? on reset por h_vbb v bb por high level detection threshold 4.5 v por l_vbb v bb por low level detection threshold 1.7 3.8 v por _vbb_sl maximum slope on v bb to guarantee por 2 v/ s thermal shutdown t j_tsd junction temperature for shutdown 165 195 c t j_hyst thermal shutdown hysteresis 9 18 c 15. measured at output voltage v cc_out = (v cc_out @ v bb = 6 v) ? 2%. 16. the voltage drop in normal mode between lin and v bb pin is the sum of the diode drop and the drop at serial pull up resistor. the drop at the switch is negligible. see figure 2. 17. guaranteed by design. not tested
ncv7425 http://onsemi.com 13 table 8. ac characteristics ? 3.3 v and 5 v versions v bb = 7 v to 18 v; t j = ? 40 c to +150 c; unless otherwise specified. symbol parameter conditions min typ max unit ac characteristics lin transmitter d1 duty cycle 1 = t bus_rec(min) / (2 x t bit ) see figure 24 normal slope mode th rec(max) = 0.744 x v bb th dom(max) = 0.581 x v bb t bit = 50 s v bb = 7 v to 18 v 0.396 0.5 d2 duty cycle 2 = t bus_rec(max) / (2 x t bit ) see figure 24 normal slope mode th rec(min) = 0.422 x v bb th dom(min) = 0.284 x v bb t bit = 50 s v bb = 7.6 v to 18 v 0.5 0.581 d3 duty cycle 3 = t bus_rec(min) / (2 x t bit ) see figure 24 normal slope mode th rec(max) = 0.778 x v bb th dom(max) = 0.616 x v bb t bit = 96 s v bb = 7 v to 18 v 0.417 0.5 d4 duty cycle 4 = t bus_rec(max) / (2 x t bit ) see figure 24 normal slope mode th rec(min) = 0.389 x v bb th dom(min) = 0.251 x v bb t bit = 96 s v bb = 7.6 v to 18 v 0.5 0.590 t fall_norm lin falling edge normal slope mode; v bb = 12 v; l1, l2 (note 18) 22.5 s t rise_norm lin rising edge normal slope mode; v bb = 12 v; l1, l2 (note 18) 22.5 s t sym_norm lin slope symmetry normal slope mode; v bb = 12 v; l1, l2 (note 18) ? 4 4 s t fall_norm lin falling edge normal slope mode; v bb = 12 v; l3 (note 18) 27 s t rise_norm lin rising edge normal slope mode; v bb = 12 v; l3 (note 18) 27 s t sym_norm lin slope symmetry normal slope mode; v bb = 12 v; l3 (note 18) ? 5 5 s t fall_low lin falling edge low slope mode (note 19); v bb = 12 v; l3 (note 18) 62 s t rise_low lin rising edge low slope mode (note 19); v bb = 12 v; l3 (note 18) 62 s t wake dominant time ? out for wake ? up via lin bus 30 150 s t dom txd dominant time ? out txd = low 6 20 ms v cc_uv_deb v cc under ? voltage detection debounce time 1.5 5 10 s r stn_ext extension time of rstn low pulse beyond v cc under ? voltage 3 6 10 ms ac characteristics lin receiver t rec_prop_down propagation delay of receiver falling edge 0.1 6 s t rec_prop_up propagation delay of receiver rising edge 0.1 6 s t rec_sym propagation delay symmetry t rec_prop_down ? t rec_prop_up ? 2 2 s 18. the ac parameters are specified for following rc loads on the lin bus: l1 = 1 k / 1 nf; l2 = 660 / 6.8 nf; l3 = 500 / 10 nf. 19. low slope mode is not compliant to the lin 1.3 or lin 2.0/2.1 standard.
ncv7425 http://onsemi.com 14 regulator typical performance characteristics (3.3 v version) load transient responses figure 8. load transient response (i cc 100 a to 100 ma) figure 9. load transient response (i cc 1 ma to 100 ma) line transient responses figure 10. line transient response (v bb 5 v to 28 v) figure 11. line transient response (v bb 5 v to 28 v)
ncv7425 http://onsemi.com 15 regulator typical performance characteristics (3.3 v version) figure 12. dropout voltage vs. temperature figure 13. output voltage vs. output current static characteristics figure 14. ground current vs. output current figure 15. output voltage vs. temperature
ncv7425 http://onsemi.com 16 regulator typical performance characteristics (5 v version) load transient responses figure 16. load transient response (i cc 100 a to 100 ma) figure 17. load transient response (i cc 1 ma to 100 ma) line transient responses figure 18. line transient response (v bb 6 v to 28 v) figure 19. line transient response (v bb 6 v to 28 v)
ncv7425 http://onsemi.com 17 regulator typical performance characteristics (5 v version) static characteristics figure 20. dropout voltage vs. temperature figure 21. output voltage vs. output current figure 22. ground current vs. output current figure 23. output voltage vs. temperature
ncv7425 http://onsemi.com 18 t bus_dom(min) lin t th rec (max) th rec (min) th dom (max) th dom (min) t bus_dom(max) t bus_rec(max) t bus_rec(min) t bit t bit 50% thresholds of receiving node 1 thresholds of receiving node 2 txd t pc20060428.2 figure 24. lin transmitter duty cycle lin t 60% 40% 60% 40% pc20060428.1 100% 0% figure 25. lin transmitter rising and falling times t fall t rise 50% t rec_prop_up rxd t lin t pc20060428.3 t rec_prop_down figure 26. lin receiver timing 60% v bb 40% v bb v bb
ncv7425 http://onsemi.com 19 ordering information device description temperature range package shipping ? NCV7425DW0G lin transceiver + 3.3 v regulator + reset pin ? 40 c to 125 c soic ? 16, wb, ep (pb ? free) 46 units / tube ncv7425dw0r2g 1500 / tape & reel ncv7425dw5g lin transceiver + 5 v regulator + reset pin 46 units / tube ncv7425dw5r2g 1500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncv7425 http://onsemi.com 20 package dimensions soic ? 16 lead wide body, exposed pad pdw suffix case 751ag issue a g ? w ? ? u ? p m 0.25 (0.010) w ? t ? seating plane k d 16 pl c m 0.25 (0.010) t uw s s m f detail e detail e r x 45 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable protrusion shall be 0.13 (0.005) total in excess of the d dimension at maximum material condition. 6. 751r-01 obsolete, new standard 751r-02. j m 14 pl pin 1 i.d. 8 1 16 9 top side 0.10 (0.004) t 16 exposed pad 18 back side l h dim a min max min max inches 10.15 10.45 0.400 0.411 millimeters b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc h 3.45 3.66 0.136 0.144 j 0.25 0.32 0.010 0.012 k 0.00 0.10 0.000 0.004 l 4.72 4.93 0.186 0.194 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 a b 9 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.350 0.175 0.050 0.376 0.188 0.200 0.074 dimensions: inches 0.024 0.150 exposed pad c l c l on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. ncv7425/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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